The present invention relates to a semiconductor device, and in particular to the semiconductor device for functioning as a neuron element, an electric potential generating device, a logic transformation circuit and so on which are elements of an artificial neural network.
Semiconductor integrated circuit technologies have made remarkable progress in recent years, and various high-performance logical integrated circuits have been developed in addition to mere memory devices. However, it may also be said that these logical circuits have not made progress as to logic since the advent of LSI in that operation is performed by using a binary signal. While a current integrated circuit is capable of performing simple numerical calculation at a very high speed as to such binary operation, it has a disadvantage that the operation rather easy for a human being such as pattern recognition or image processing takes an enormous amount of time.
On the other hand, there is an ongoing research wherein, as the element capable of performing at a high speed this operation not suited to the LSI in the past, attempts are made to develop a computer for operating like brains of a living creature, that is, a neuro-computer. This neuro-computer has a structure in which a large number of neuron elements are connected like a neural network.
The neuron elements in the past were mostly manufactured with a CMIS device, and in that case, there is no learning ability of changing the operation of the circuit by learning. For instance, in Japanese Patent No. 3122756 specification, there is a description of a MIS type neuron element having a large number of input portions placed for capacity coupling to a gate electrode of MISFET. While this performs the operation of adding a product of signal strength and coupling strength of each of a plurality of input terminals by the number of the input portions by utilizing the capacity coupling, there is no function of storing operation results as a learning effect.
As opposed to it, in recent years, a proposal has been made, which is related to a first past example for implementing the learning ability by using residual polarization of a ferroelectric. For instance, in Japanese Patent No. 2929909 specification, there is a description that all the capacitive dielectric films of the input portions are comprised of the ferroelectric in the MIS type neuron element having a plurality of input portions placed for capacity coupling to the gate electrode of the MISFET. In addition, in Japanese Patent No. 2942088 specification, there is a description of the element of which gate dielectric film of the MISFET on an output side is comprised of the ferroelectric in the MIS type neuron element having a plurality of input portions placed for capacity coupling to a gate electrode of the MISFET.
In addition, the LSI is making very rapid progress, and a transistor is increasingly rendered finer and more highly integrated. However, it is becoming difficult to improve yields because of the finer transistor and enormous chip area. In addition, as a circuit scale has become very large-scale and the system LSI of flexible production is mainstream, design thereof requires considerable personnel and time. For this reason, it is no longer easy to shorten a development period. To solve such a problem, a reconfigurable circuit is receiving attention. The reconfigurable circuit is a circuit capable of rewriting in conjunction with change in circuit specifications after manufacturing the LSI. As an example thereof, an FPGA (Field Programmable Gate Array) or a CPLD (Complex Programmable Logic Device) can be named. These are capable of implementing a changeable logic circuit by combining basic logical blocks in multiple stages. To be more specific, in this FPGA/CPLD, a switch element and a multiplexer are used as program elements, and the function is determined therewith by a combination of basic logic circuits. As for these methods, however, the area occupied by a redundant circuit of the basic logical block is so large that wiring becomes long. On the other hand, there is a proposal of the element wherein the program element itself is capable of converting the logic by using the ferroelectric ([61th Applied Physics Society Academic Lecture Manuscripts 6a-g-1. Naoichi Kawaguchi, Seimin In, Eisuke Tokumitsu])
FIG. 40 is an equivalent circuit diagram of the neuron element related to the second past example described in the above patent journal. In this example, a residual electric charge is generated by a pulse signal in a ferroelectric capacitor, and this residual electric charge is utilized to control an electric potential of a floating gate so as to attempt implementation of the logic transformation circuit of an NOR circuit and an NAND circuit.
As shown in FIG. 40, this neuron element has an n-channel type MIS transistor (NMISFET 510). Here, the gate electrode of the NMISFET 510 is a floating gate 506 which is connected to no other terminal and is in a floating state. A source is grounded, and a drain is connected to an output terminal 509. The output terminal 509 is connected to a power supply voltage supply terminal 507 for supplying power supply voltage VDD via a load resistance element 508.
In addition, it has two input terminals 500 and 501 for capacity coupling to the floating gate 506, paraelectric capacitors 503 and 504 intervening between the input terminals 501, 502 and the floating gate 506, a control terminal 502 for receiving a control signal, and a ferroelectric capacitor 505 intervening between the control terminal 502 and the floating gate 506.
Here, the logic of an input signal from the input terminal 500 is X1, the input signal from the input terminal 501 is X2, a charge amount of the control terminal 502 is CR, the charge amount of the floating gate 506 is φF, and the logic of an output signal from an output terminal 509 is Y. In addition, a threshold voltage of the NMISFET 510 is 0 V. Furthermore, when X1 and X2 are “1,” the charge amount Q0 is induced to an upper electrode (the electrode on the input terminal side) of each of the paraelectric capacitors 503 and 504.
FIG. 41 is a diagram showing as a table the charge amounts of the portions against the input signals X1 and X2 on adding a negative pulse signal to the control terminal 502 and logical values of an output signal Y.
First, the negative voltage pulse signal is added to the control terminal 502 so as to generate the residual electric charge of the charge amount of −Q/2 on the upper electrode of the ferroelectric capacitor 505. At this time, the charge amount φF of the floating gate 506 is as shown in FIG. 41. If the charge of the floating gate 506 is positive at this time, a channel is formed on a SiO2/Si interface and a MOS transistor is ON so that an output value Y is the value shown in FIG. 41. As is understandable from FIG. 41, a circuit operation at this time is an NOR circuit operation.
FIG. 42 is a diagram showing as a table the charge amounts of the portions against the input signals X1 and X2 on further adding a negative pulse signal of a larger amplitude to the control terminal 502 and logical values of the output signal Y.
First, the negative voltage pulse signal of a larger amplitude is further added to the control terminal 502 so as to generate the residual electric charge of the charge amount of −3Q0/2 on the upper electrode of the ferroelectric capacitor 505. At this time, the charge amount φF of the floating gate 506 is as shown in FIG. 42.
If the charge of the floating gate 506 is positive, the channel is formed on the SiO2/Si interface and the NMISFET 510 is ON so that the output value Y is the value shown in FIG. 42. As is understandable from FIG. 42, the circuit operation at this time is an NAND circuit operation. Thus, it is possible, by controlling the residual electric charge of the ferroelectric capacitor, to implement the program element which is the logic transformation circuit of the NOR circuit and the NAND circuit.
In addition, as a third past example, the neuro-computer in the past will be described. To describe the operation of the neuro-computer, the operation of the brains of the living creature which were a model thereof will be simply described first.
FIG. 44 is a block diagram showing configuration of a basic unit of the brains which is simplified. In this diagram, reference numerals 601a, 601b and 601c denote neurons, and reference numerals 602a, 602b and 602c denote nerve cells. 603a, 603b and 603c are called synapse couplings, which multiply the signal conveyed by the nerve cell 602a by a load wa for instance and input it in the neuron 601a. The neuron 601a takes a linear sum of the signal strength which is inputted, and the nerve cell is activated (ignited) if the sum thereof exceeds a certain threshold and outputs the signal to the nerve cell 602b. If the sum thereof is equal to or less than the threshold, the neuron does not output the signal. It is said that, as plenty of such comparatively simple sum of products operations are processed in parallel, information processing unique to the brains is implemented.
Such a research in the operation of the neuron was actively conducted as the software in the past. On the other hand, there is also a trend to try to implement high-speed operation and so on by implementing and optimizing this neuron function with hardware. As an example of such neuron element development, the neuron MOSFET (abbreviated as νMOS) can be named, which is described in Japanese Patent No. 2662559 specification.
FIG. 45 is a schematic diagram showing the structure of the νMOS related to the third past example which is simplified. As shown in this diagram, the νMOS has floating gates FG which are the gate electrodes of a field effect transistor (MISFET), and also has the configuration wherein a plurality of capacitor CGs of which lower electrodes are the floating gates FG are mutually connected in parallel. As such configuration renders the gate portion of the νMOS as the configuration wherein capacitors CG and CO are serially connected, the signals (voltages) inputted in input terminals G1 to G4 are distributed so that a larger voltage is distributed to the gate portion of the νMOS of a smaller capacity based on the voltage distribution principle of the serial capacitors. As the sum of the signals inputted in the input terminals G1 to G4 increases, the voltage distributed to the gate portion becomes higher and a drain current of the νMOS increases.
This operation allows the above-mentioned neuron operation of the brains to be represented as an element operation of the semiconductor device.
On the other hand, another function is required in the case of implementing the functions of the brains. It is the function described as the synapse in FIG. 44, which is the function of implementing load of a plurality of inputs intervening for one neuron respectively. As a past example of the neuron element of the neuro-computer having such a load function, there is a technology described in Japanese Patent No. 3122756 specification for instance.
FIG. 46 is a schematic diagram showing the configuration of the neuron element of the past example described in the patent journal. In this diagram, 611 and 612 are NMOS and PMOS transistors respectively. A floating gate 613 is provided on an NMOS channel area via a gate oxide film. In addition, the floating gate 613 is opposite a charge injection electrode 616 via a SiO2 film of approximately 5 to 7 nm. A wiring 617 is the gate electrode of the PMOS transistor 611, and is capacity-coupling with the floating gate of the NMOS transistor 611 via the SiO2 film of approximately 20 nm thickness at the same time, also having the function of the gate electrode of the NMOS transistor 611. Reference numeral 620 denotes the wiring. An electrode 621 is capacity-coupling with the floating gate 613 via the SiO2 film of approximately 20 nm thickness. A neuron circuit 217 has a large number of input terminals 218a to 218d. 
The neuron element of the past shown in FIG. 46 changes the electric potential of the floating gate 613 by injecting the charge into the floating gate 613 from the charge injection electrode 616 by means of a tunnel current. It is thereby possible to change the threshold voltage of the NMOS transistor 611. This effect allows the signal (voltage) inputted from a wiring 619 via the wiring 617 to change a voltage level for rendering the NMOS transistor 611 in a conductive state. It just means that the influence exerted by the input signal upon the ON (ignition) of the neuron circuit is changed, which implements the synapse operation for changing the load. Moreover, the synapse circuit of the embodiment in the above patent journal is constituted by combining the NMOS transistor 611 and the PMOS transistor 612, and so the outputs are two values of a VDD and a GND (0 V).
In order to correctly control the charge amount of the tunnel current for setting such a load coefficient, this past example not only changes an absolute value of an injection control voltage, but also changes the injection control voltage like a pulse or controls it by a pulse width, a pulse height or the pulse number.
In addition, as for means for changing the threshold voltage of the NMOS transistor in the above past example, a nonvolatile memory element using a ferroelectric film (ferroelectric gate transistor) may be used other than the above-mentioned floating gate type MOS transistor.
FIG. 47 is a sectional view showing the ferroelectric gate transistor structure described in the above patent journal. In this diagram, reference numeral 656 denotes a P type Si substrate, and 657 denotes the SiO2 film of 5 nm for instance. Reference numeral 658 denotes the ferroelectric film, which uses a PZT (Pb (ZrxTi1-x) O2) of 300 nm film thickness for instance. Reference numeral 659 denotes the electrode of Ti for instance. Reference numerals 660a and 660b denote N+ type source and drain. In this patent, the ferroelectric film is polarized by adding a positive or negative pulse to a gate electrode 659, and the threshold voltage of the transistor is controlled according to the size of the polarization.
However, there were the following problems in the above first past example.
First, as for the neuron element, it is necessary, in the case where “1” or “0” is outputted from the neuron to a certain input, to render the same output easier from the next time. To be more specific, it is necessary to learn and store output situation of each neuron. Nevertheless, the MIS type neuron element described in Japanese Patent No. 2929909 specification can learn and store that the input portion of each neuron became 1” or “0” from the residual polarization of the ferroelectric film provided in each input portion, but it cannot learn and store the information that the neuron outputted “1” or “0”. It is because it cannot uniquely determine whether the output will be “1” or “0” even if some input portions are “1”.
Secondly, in the case of providing the learning ability to the neuron element, it is desirable to add the function of resetting or weakening the learning ability. As the MIS type neuron element described in Japanese Patent No. 2942088 specification has the gate dielectric film of the MISFET on the output side comprised of the ferroelectric, it is capable of learning and storing the output state of the neuron, which is the first problem. However, in order to reset or weaken this learning and storing function, it is necessary to change the polarization of the ferroelectric film by applying between the substrate and the gate electrode the voltage of a polarity different from ordinary operation of the MISFET. It is necessary, for this purpose, to electrically insulate the substrate portion of each MIS type neuron element, which renders it very complicated including the control circuit.
In addition, as for the neuron element for functioning as the logic transformation circuit (program element) related to the above second past example, there was a problem that the residual electric charge generated on the ferroelectric film of the ferroelectric capacitor 505 is influenced by the electric potential φF of the floating gate 506.
Here, if the voltage applied to the ferroelectric film (the control terminal side is positive) is Vferr, Vferr is represented by the following equation (101).Vferr=CR−φF=−φF  (101)
Here, it is further considered by paying attention to the region in which the pulse signal is not applied to the control terminal 502. At this time, it is understandable from the formula (101) that the voltage applied to the ferroelectric film is dependent on the electric potential φF of the floating gate 506. As φF changes according to the input, the voltage applied to the ferroelectric film from the formula (101) must change. Thus, there was a problem that the residual electric charge induced to the ferroelectric film changes. This problem will be described by referring to the diagram.
FIGS. 43A and B are timing charts showing time variation of the electric potential of the floating gate and the timing chart showing the time variation of the voltage applied to the ferroelectric film of the neuron element related to the above second past example in order respectively. Here, a voltage value of the logical value “0” is 0 V, and voltage value of the logical value “1” is 5 V. After inputting (0, 0), (1, 1), (0, 1) and (1, 0) in the input terminals 500 and 501 respectively, the pulse signal of −10 V is applied to the control terminal 502 and the residual electric charge is induced to the ferroelectric capacitor 505. Thereafter, (0, 0), (1, 1), (0, 1) and (1, 0) are repeatedly inputted in the input terminals 500 and 501 respectively.
At this time, as is also understandable from FIG. 43A, the voltage applied to the ferroelectric film is also changing in the region to which no pulse signal is added. To be more specific, as shown in a region Rx in FIG. 43A, the electric potential φF of the floating gate 506 for the input (0, 1) before the pulse signal is inputted and the electric potential φF for the input (1, 0) are mutually different. This is because, as previously mentioned, if the input signal is applied to the input terminal, the voltage applied to the ferroelectric film of the ferroelectric capacitor changes. In addition, as shown in a region Ry in FIG. 43A, the electric potentials φF of the floating gate for the same input of the first time and second time are mutually different after the pulse signal is applied to the control terminal 502. It is also because, if the voltage is applied to the input terminal, the voltage applied to the ferroelectric film of the ferroelectric capacitor does not remain invariant and consequently the residual electric charge of the ferroelectric capacitor changes.
Thus, as for the neuron element for functioning as the logic transformation circuit of the NOR circuit and the NAND circuit of the above second past example, there was a problem that the residual electric charge of the ferroelectric capacitor changes due to the voltage applied to another input terminal, and consequently the residual electric charge induced on the ferroelectric capacitor cannot be stably held so that a logic transformation function becomes unstable.
In addition, as for the configuration using the tunnel current shown in FIG. 46 which is a first technique for constituting the synapse circuit of the neuro-computer related to the above third example, it is very difficult, considering that the tunnel current exponentially changes against the field strength, to control a tunnel charge amount by the pulse width, the pulse height and the pulse number.
FIG. 48 is a diagram showing a correlation between the applied voltage and the tunnel current when an electron tunnels through a thermal oxidation silicon film of 10 nm thickness. As shown therein, the tunnel current has a nature of exponentially increasing, and so it is easily understood that controllability of the charge to a floating electrode in the past example is very difficult. As a result of it, it was difficult to set the load coefficient in multiple stages and with high accuracy. As accuracy is required for setting of the load coefficient in an operation process of the neural network, delicate setting of the load coefficient is very difficult with the technique in FIG. 46, and consequently there is a problem that the neuron element does not properly operate so that the learning does not easily converge, for instance. In addition, there is also a problem that the field strength capable of effectively using a tunnel phenomenon with the device is approximately 6 MV/cm or more and consequently a very high driving voltage is necessary.
Furthermore, a ferroelectric gate transistor which is a second technique for constituting the synapse circuit as shown in FIG. 47, there is no concrete means prepared such as a specific wiring connection form and an application method of the driving voltage, and so it is questionable whether the proper operation as the synapse can be obtained.